The most successful semiconductor companies know that the increasing complexity of integrated circuit (IC) designs is straining our traditional design rule checking (DRC) methods. The iterative “construct by correction” approach that worked well for simpler, custom layouts is now creating substantial runtime and resource bottlenecks, hindering design teams’ ability to efficiently verify their advanced designs and meet aggressive time-to-market targets. To outpace this design complexity, major semiconductor companies constantly look for effective tools from its ecosystem partners. Siemens EDA, a major electronics design automation (EDA) company offered a new and powerful shift-left verification strategy, they evaluated it and declared it a game-changer for their early design stages.
How shift-left addresses the challenges of modern IC design
The electronics industry is constantly on the move, innovating and changing fundamental aspects of integrated circuits. The entire ecosystem reacts and drives improvements that lead to ever faster, smaller and more powerful ICs. For the physical design and verification of layouts before manufacturing, we could once rely on a manual, custom process. This has given way to highly automated workflows and multi-layered design hierarchies. Because different design components are developed by disparate design teams on different timelines, it has become extremely difficult to have a fully assembled design layout available for comprehensive verification. Additionally, the sheer volume and complexity of today’s advanced process design rules have exacerbated the runtime and compute requirements for the crucial design rule checks (DRC) that are required before manufacturing.
The solution lies in shifting verification steps earlier in the design process - a strategy known as “shift-left” verification. By moving verification closer to the source of design changes, shift-left approaches can significantly reduce debug time, manage incomplete data and expedite the path to tape-out. The runtime and memory difference between a traditional DRC run and a shift-left DRC run is significant, as shown in figure 1.
Figure 1. Runtime and memory improvements of Calibre nmDRC Recon (orange bars) compared to Calibre nmDRC (blue bars).Siemens EDA
Major semiconductor companies are having success with the shift-left DRC tool from Siemens EDA, called Calibre DRC Recon. The key to this tool’s effectiveness lies in its ability to identify and run only the rules that are local in scope, rather than executing a comprehensive DRC check across the entire design. This “local checks” approach drastically reduces runtime and hardware requirements compared to traditional DRC methods.
Complementing the local checks approach, designers can also use an auto-waivers feature to identify and exclude regions of the design that are known to be incomplete, eliminating them from checking so false violations don’t slow down the verification process. This is a grey-boxing technique achieved with auto-waivers as illustrated in figure 2.
A customer’s shift-left DRC success story
A leading technology company has seen firsthand the benefits of adopting a shift-left verification strategy using Calibre DRC Recon. The design team was able to significantly reduce runtime and hardware requirements while enhancing their overall productivity. The designers started using Calibre nmDRC Recon iterations at the floorplan stage, then at the physical implementation stage. By that point, most of the designs were clean of shorts on power and ground nets. They were able to catch any issues early, while they were still easy to fix through directly in their layout environment. Because these fixes were made using the sign-off accurate Calibre rules, the team knew that the results were reliable and highly accurate. Figure 3 illustrates runtime improvements for different DRC methods.
Figure 3. Run times are significantly reduced when using shift-left DRC.Siemens EDA
The designer’s experience demonstrates the power of shift-left verification in action. By leveraging the local checks approach and complementary features like auto-waivers and split-deck runs, the team was able to accelerate their design iterations and reduce time-to-market.
The runtime improvements were substantial, with the shift-left DRC tool delivering up to 15 times faster performance compared to traditional DRC methods. Moreover, the memory usage was reduced by up to 18 times, allowing the design team to maximize the utilization of their compute resources.
Embracing the shift-left mindset for faster IC design
As the complexity of IC designs continues to escalate, design teams can no longer rely on traditional DRC methods to keep pace. The shift-left verification strategy offers a compelling solution that addresses the key challenges faced by modern design organizations.
By focusing on local checks, leveraging auto-waivers, and optimizing parallel execution, shift-left DRC accelerates the design and verification process, simplifies debugging and ultimately, brings innovative products to market faster. The case study serves as a powerful testament to the transformative impact of this approach, highlighting the significant productivity gains and efficiency improvements that design teams can achieve.
Embracing a shift-left mindset for physical verification will be crucial for design teams looking to stay ahead of the curve. The advanced DRC tool from Siemens EDA provides a proven path forward, equipping designers with the capabilities they need to navigate the complexities of modern IC design and deliver their cutting-edge products to the market with unprecedented speed and efficiency.
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