Last week at the IEEE International Solid State Circuits Conference, two of the biggest rivals in advanced chipmaking, Intel and TSMC, detailed the capabilities of the key memory circuits, SRAM, built using their newest technologies, Intel 18a and TSMC N2. Chipmakers’ ability to keep scaling down circuits has slowed over the years—but it’s been particularly difficult to shrink SRAM, which is made up of large arrays of memory cells and supporting circuits.
The two companies’ most densely packed SRAM block provides 38.1 megabits per square millimeter, using a memory cell that’s 0.021 square micrometers. That density amounts to as much as a 23 percent boost for Intel and a 12 percent improvement for TSMC. Somewhat surprisingly, that same morning Synopsys unveiled an SRAM design that achieved the same density using the previous generation of transistors, but it operated at less than half the speed.
The Intel and TSMC technologies are the two companies’ first use of a new transistor architecture, called nanosheets. (Samsung transitioned to nanosheets a generation earlier.) In previous generations, current flows through the transistor via a fin-shaped channel region. The design means that increasing the current a transistor can drive—so that circuits can operate faster or involve longer interconnects—requires adding more fins to the device. Nanosheet devices do away with the fins, exchanging them for a stack of silicon ribbons. Importantly, the width of those nanosheets is adjustable from device to device, so current can be increased in a more flexible fashion.
“Nanosheets seem to allow SRAM to scale better than in other generations,” says Jim Handy, chief analyst memory consulting firm Objective Analyst.
Flexible transistors make smaller, better SRAM
An SRAM cell stores a bit in a six-transistor circuit. But the transistors are not identical, because they have different demands on them. In a FinFET-based cell, this can mean building two pairs of the devices with two fins each and the remaining two transistors with one fin each.
Nanosheet devices provide “more flexibility on the size of the SRAM cell,” says Tsung-Yung Jonathan Chang, a senior director at TSMC and an IEEE Fellow. There is less unintended variation among transistors with nanosheets, he says, a quality that improves SRAM’s low-voltage performance.
Engineers from both companies took advantage of nanosheet transistors’ flexibility. For the previously twin-finned devices, called the pull down and pass gate transistors, nanosheet devices could be physically narrower than the two separate fins they replaced. But because the stack of nanosheets has more silicon area in total, it can drive more current. For Intel that meant up to a 23 percent reduction in cell area.
“Typically, the bit line has been stuck at 256 bits for a while. For N2… we can extend that to 512. It improves the density by close to 10 percent.” —Tsung-Yung Jonathan Chang, TSMC
Intel detailed two versions of the memory circuit, a high-density and a high-current version, and the latter took even more advantage of nanosheet flexibility. In FinFET designs, the pass gate and pull down transistors have the same number of fins, but nanosheets allow Intel to make the pull-down transistors wider than the pass-gate devices, leading to a lower minimum operating voltage.
In addition to nanosheet transistors, Intel 18a is also the first technology to include backside power delivery networks. Until 18a, both power delivery interconnects, which are typically thick, and signal-carrying interconnects, which are finer, were built above the silicon. Backside power moves the power interconnects beneath the silicon where they can be larger and less resistant, powering circuits through vertical connections that come up through the silicon. The scheme also frees up space for signal interconnects.
With FinFET devices, an SRAM’s pass gate (PG) and pull down (PD) transistors need to drive more current than other transistors, so they are made with two fins. With nanosheet transistors, SRAM can have a more flexible design. In Intel’s high-current design, the PG device is wider than others, but the PD transistor is even wider than that to drive more current. Intel
However, backside power is no help in shrinking the SRAM bit cell itself, Xiaofei Wang, technology lead and manager at Intel, told engineers at ISSCC. In fact, using backside power within the cell would expand its area by 10 percent, he said. So instead, Intel’s team restricted it to peripheral circuits and to the perimeter of the bit cell array. In the former, it helped shrink circuits, because engineers were able to build a key capacitor beneath the SRAM cells.
TSMC is not yet moving to backside power. But it was able to extract useful circuit-level improvements from nanosheet transistors alone. Because of the transistor flexibility, TSMC engineers were able to extend the length of the bit line, the connection through which cells are written to and read. A longer bit line links more SRAM cells and means the memory needs fewer peripheral circuits, shrinking the overall area.
“Typically, the bit line has been stuck at 256 bits for a while,” says Chang. “For N2… we can extend that to 512. It improves the density by close to 10 percent.”
Synopsys squeezes SRAM circuits
Synopsys, which sells electronics design automation tools and circuit designs that engineers purchase and integrate into their systems, reached roughly the same density as TSMC and Intel but using today’s most advanced FinFET technology, 3-nanometer. The company’s density gain came mainly from the peripheral circuits that control the SRAM array itself, specifically what’s called an interface dual-rail architecture combined with an extended-range level shifter.
To save power, particularly in mobile processors, designers have begun to drive the SRAM array and the peripheral circuits at different voltages, explains Rahul Thukral, senior director of product management at Synopsys. Called dual rail, it means that the periphery can operate at a low voltage when needed while the SRAM bit cells run at a higher voltage, making it less likely they will lose their bits.
But that means the voltages representing the 1s and 0s in the SRAM cells don’t match the voltages in the periphery. So, designers incorporate circuits called level shifters to compensate.
The new Synopsys SRAM improves the memory’s density by placing the level shifter circuits at the interface with the periphery instead of deep within the cell array and by making the circuits smaller. What the company is calling “extended range level shifters” integrate more functions into the circuit while using FinFETs with fewer fins, leading to a more compact SRAM overall.
But the density isn’t the only point in its favor, according to Thukral. “It allows the two rails to be very much further apart,” he says, referring to the bit cell voltage and the periphery voltage. The voltage at the bit cells can run between 540 millivolts and 1.4 volts while the voltage at the periphery can go as low as 380 mV. That voltage difference allows the SRAM to perform well while minimizing power, he says. “When you bring it down to really, really low voltages… it brings power down by a lot, which is what today’s AI world loves,” he says.
Asked if a similar circuit design might work to shrink SRAM in the future nanosheet technologies, Thukral said: “The answer is 100 percent yes.”
Although, Synopsys managed to match TSMC and Intel on density, its offering operated much more slowly. The Synopsys SRAM’s maximum was 2.3 gigahertz compared to 4.2 GHz for the fastest version of TSMC’s SRAM and 5.6 GHz for Intel’s.
“It’s impressive Synopsys can reach the same density on 3 nm, and it’s at a frequency that will be relevant for the mass market silicon for that node in the long term,” says Ian Cutress, chief analyst at More Than Moore. “It also showcases how process nodes are rarely static, and new, dense designs for things like SRAM are still occurring.”
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