It says something about your career at a company that makes hundreds of trillions of transistors every day when your nickname is “Mr. Transistor.” That’s what colleagues often call Tahir Ghani, a senior fellow and the director of process pathfinding in Intel’s technology development group. Ghani’s career spans three decades at the company and has resulted in more than a thousand patent filings. He’s had a hand in every major change to the CMOS transistor during that time period.
As Intel heads toward yet another major change—the move from FinFETs to RibbonFETs (called nanosheet transistors, more generically)—IEEE Spectrum asked Ghani what’s been the riskiest change so far. In an era when the entire architecture of the device has morphed, his somewhat surprising answer was a change introduced back in 2008 that left the transistor looking—from the outside—pretty similar to how it did before.
3 Big Changes to the Transistor
Prior to this year’s introduction of RibbonFETs, there have been three major changes to the CMOS transistor. At the turn of the century, the devices looked pretty much like they always had, just ever smaller. Built into the plane of the silicon are a source and drain separated by the channel region. Atop this region is the gate stack—a thin layer of silicon oxide insulation topped by a thicker piece of polycrystalline silicon. Voltage at the gate (the polysilicon) causes a conductive channel to bridge the source and drain, allowing current to flow.
But as engineers continued to shrink this basic structure, producing a device that drove enough current through it—particularly for the half of devices that conducted positively-charged holes instead of electrons—became more difficult. The answer was to stretch the silicon crystal lattice somewhat, allowing charge to speed through faster. When Intel announced its strained-silicon plan back in 2002, this was done by adding a bit of silicon germanium to the source and drain, and letting the material’s larger crystal structure squeeze the silicon in the channel between them.
The thin layer of silicon dioxide insulation separating the gate from the channel was now just five atoms thick
In 2012, the FinFET arrived. This was the biggest structural change, essentially flipping the device’s channel region on its side so that it protrudes like a fin above the surface of the silicon. This was done to provide better control over the flow of current through the channel. By this point, the distance between the source and drain had been reduced so much that current would leak across even when the device is supposed to be off. The fin structure allowed chipmakers to drape the gate stack over the channel region so that it surrounds the channel region on three sides, which gives better control than the planar transistor’s single-sided gate.
But between strained silicon and the FinFET came Intel’s riskiest move, according to Ghani—high-k/metal gate.
Running Out of Atoms
“If I take the three big changes in transistors during that decade my personal feeling is that high-k/metal gate was the most risky of all,” Ghani told IEEE Spectrum at the IEEE International Electron Device Meeting in December. “When we went to high-k/metal gate, that is taking the heart of the MOS transistor and changing it.”
As Tahir and his colleagues put it in an article in IEEE Spectrum at the time: “The basic problem we had to overcome was that a few years ago we ran out of atoms.”
Keeping to Moore’s Law scaling in this era meant reducing the smallest parts of a transistor by a factor of 0.7 with each generation. But there was one part of the device that had already reached its limit. The thin layer of silicon dioxide insulation separating the gate from the channel, having been thinned down 10-fold since the middle of the 1990s, was now just five atoms thick.
Losing any more of the material was simply impossible, and worse, at five atoms the gate dielectric was barely doing its job. The dielectric is meant to allow voltage at the gate to project an electric field into the channel but at the same time keep charge from leaking between the gate and the channel.
“We initially wanted to do one change at a time,” recalls Ghani, starting with swapping the silicon dioxide for something that could be physically thicker but still project the electric field just as well. That something is termed a high-dielectric-constant, or high-k, dielectric. When Intel’s components research team looked at doing that, Ghani says, “they found that actually if you just do polysilicon with high-k, there is an interaction between the poly and high-k.” That interaction effectively pins the voltage at which the transistor turns on or off—the threshold voltage—at a worse value than if you’d left well enough alone.
“There was no way out except… to do a metal gate too,” Ghani says. Metal would bond better to the high-k dielectric, eliminating the pinning problem while solving some other issues along the way. But finding the right metal—two metals really, because there are two types of transistor, NMOS and PMOS—introduced its own problems.
“Like a dog to a bone, the whole organization was psyched up to do it.” —Tahir Ghani, Intel
“The problem with the metal gate was that all the materials that would have [worked]… cannot withstand high temperatures” needed to build the rest of the device, Ghani says.
Once again, the solution actually ratcheted up the risk even further. Intel would have to take the series of steps it had reliably used to build transistors for 30 years and reverse it.
The basic process involved building the gate stack first and then using its dimensions as the boundaries around which the company built the rest of the device. But the metal gate stack wouldn’t survive the extremes of this so-called gate first process. “The way out was we had to reverse the flow and do the gate at the end,” explains Ghani. The new process, called gate last, involved starting with a dummy gate, a block of polysilicon, continuing with the processing, then removing the dummy and replacing it with the high-k dielectric and the metal gate. Adding yet a further complication, the new gate stack had to be deposited using a tool that Intel had never used in chip production called atomic-layer deposition. (It does what the name implies.)
“We had to change the foundational flow we had done for so many decades,” says Ghani. “We put in all these new elements and changed the heart of the transistor; we started to use tools we had not done before in industry. So if you look at the plethora of challenges that we had, I think it was clearly the most challenging project I have worked on.”
The 45-nanometer Node
That wasn’t the end of the story, of course.
The new process had to reliably produce devices and circuits and complete ICs with a degree of reliability that would ensure its economical use. “It was such a big change, we had to be very careful,” Ghani says. “And so we took our time.” Intel’s team developed processes for both NMOS and PMOS, then built wafers of each device separately, then together before moving on to more complex things.
Even then, it wasn’t clear that high-k/metal gate would make it as Intel’s next manufacturing process, the 45-nanometer node. All the work to that point had been done using the design rules—transistor and circuit geometries—for the existing 65-nanometer node rather than a future 45-nanometer node. “Every time you go to new design rules there are problems that the design rules bring itself,” he explains. “So you don’t want to confuse high-k/metal gate problems and design rule issues.”
“I think it almost took us a year and half before we thought we were ready to get the first yield lot out,” he says, referring to wafers with real CPUs on instead of just test structures [CK].
“The first… lot was exceptionally good for the very first time,” recalls Ghani. Seeing how high the initial yield was and looking at how much time the team had before it needed to deliver a 45-nanometer node management committed to making high-k/metal gate it’s next production technology. “Like a dog to a bone, the whole organization was psyched up to do it,” he says.
Asked if he still thinks Intel is as adventurous as it was when it developed and deployed high-k/metal gate, Ghani responds in the affirmative. “I think we still are,” he says, giving the example of the recent deployment of back side power delivery—a technology that saves power and boost performance by moving power-delivering interconnect beneath the transistors. “Seven or eight years ago we decided to really look at back-side contacts for power delivery, and we kept on pushing.”
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